The invention relates generally to a method of fabricating a semiconductor device and, more particularly, to a method of doping p-type impurity ions in a dual poly gate and a method of forming a dual poly gate using the same.
As the degree of integration of semiconductor devices has increased, use of a complementary metal oxide semiconductor (CMOS) transistor in which a p-type MOS transistor and an n-type MOS transistor are disposed on the same substrate has gradually widened. In a general CMOS transistor, the p-type MOS transistor has a buried channel structure. In the case of the buried channel structure, increase in degree of integration of a device leads to a decrease in channel length, which in turn leads to an increase in the influence of an applied electric field, consequently resulting in deterioration of leakage current properties. Accordingly, a dual gate structure is employed to form a p-type MOS transistor of a surface channel structure. In a dual gate structure, a p-type impurity region, e.g., a p-type gate implanted with boron (B) is disposed in a region formed with the p-type MOS transistor, and an n-type impurity region, e.g., an n-type gate implanted with phosphorus (P) is disposed in a region formed with the n-type MOS transistor.
In a conventional method of forming the dual gate structure, a gate insulation layer is formed on a semiconductor substrate and a polysilicon layer is formed thereon as a gate conductive layer. N-type impurity ions are doped when forming the polysilicon layer. Next, an ion implantation process using a photoresist layer pattern, which exposes the p-type MOS transistor region, is used to implant the p-type impurity ions into a portion of the polysilicon layer corresponding to the p-type MOS transistor region. The p-type impurity ions are implanted using plasma doping. By such ion implantation, the conductivity type of the polysilicon layer in the p-type MOS transistor region is converted from an n-type into a p-type. After that, a diffusion of the impurity ions by a thermal process is implemented to form an n-type conductive poly gate in the n-type MOS transistor region and a p-type conductive poly gate in the p-type MOS transistor region.
FIGS. 1A and 1B are graphs showing concentration profiles of p-type impurity ions using the plasma doping method. Specifically, FIG. 1A is a graph showing variation in concentration profile according to increase in energy, and FIG. 1B is a graph showing variation in concentration profile according to increase in ion (i.e., impurity) dosage. As indicated by an arrow 110 in FIG. 1A, a concentration profile is such that implanted ion concentration on the surface does not vary (see “A” in FIG. 1A) but slope varies as energy is increased. Also, as indicated by an arrow 120 in FIG. 1B, the concentration profile is such that implanted ion concentration uniformly increases as dosage increases.
As described above, when using the plasma doping method, it is not easy to make a uniform implanted ion concentration profile in the polysilicon layer. One cause of this problem is that there is no projected range Rp, i.e., a mean penetration depth of impurity ions, in the plasma doping method. Since it is difficult to properly adjust the doping profile as described above, deterioration of poly depletion rate (PDR) in the p-type MOS transistor region occurs when the concentration of the p-type impurity ions is low, particularly in a portion adjacent to a gate insulation layer. The deterioration of the poly depletion rate property exhibits the same effect as an increase in a thickness of a gate oxide layer, which deteriorates operation properties of a device. When increasing energy or concentration of the p-type impurity ions in a portion adjacent to the gate insulation layer to restrict this phenomenon, a problem can occur in that the depth to which the p-type impurity ions penetrate increases and the p-type impurity ions thus penetrate into the gate insulation layer under the polysilicon layer as indicated by “B” in FIGS. 1A and “C” in FIG. 1B.